A field programmable gate array is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a field programmable gate array, the user configures an on-chip interconnect structure of the field programmable gate array so that selected inputs and selected outputs of selected on-chip logic components are connected together in such a way that the resulting circuit is the user-specific circuit desired by the user. For additional background on antifuse-based field programmable gate array structures, the reader is referred to: U.S. Pat. Nos. 5,495,181, 5,424,655, 5,122,685, 5,327,024, 5,055,718, 4,873,459; U.S. patent application Ser. No. 08/677,783 entitled "Interface Cell For A Programmable Integrated Circuit Employing Antifuses," filed Jun. 21, 1996 by Paige A. Kolze et al., now U.S. Pat. No. 5,900,742, issued May 4, 1999; the 1994 QuickLogic Data Book; the 1996 Actel FPGA Data Book and Design Guide; and the book entitled "Field-Programmable Gate Arrays" by Stephen Brown et al., Kluwer Academic Publishers (1992) (the subject matter of these documents is incorporated herein by reference).
FIG. 1 (Prior Art) is a top down diagram of a field programmable gate array (FPGA) 1 including a logic array 2, programming control circuits 3, output drivers 4 and output terminals 5, a supply voltage power input terminal (VCC) 6, a ground terminal (GND) 7, and a high voltage compatibility power input terminal (HVC) 8. Logic array 2 includes a plurality of logic modules 9 arranged in rows and columns as well as a programmable interconnect structure 10 employing antifuses disposed in the spaces between the logic modules. Antifuses in the interconnect structure are programmed by putting the FPGA into a programming mode and then loading programming data serially from a terminal (not shown) of the FPGA into the programming control circuits 3. The programming control circuits 3 cause a programming voltage Vpp (for example, 10.5 volts) received on a programming voltage terminal VPP (not shown) of the FPGA to be imposed across a selected antifuse in the interconnect structure such that the antifuse "programs" to form a permanent low resistance connection between two signal conductors of the interconnect structure. The antifuses to be programmed to realize the user-specific circuit are programmed under the control of the programming control circuits. For additional background on the structure of the programming control circuits and associated programming structures and methods, the reader is referred to: U.S. patent application Ser. No. 08/667,702 entitled "Programming Architecture For A Programmable Integrated Circuit Employing Antifuses", filed Jun. 21, 1996 by Paige A. Kolze, now U. S. Pat. No. 5,825,201, issued Oct. 20, 1998 (the subject matter of which is incorporated herein by reference).
FIG. 2 (Prior Art) is a simplified diagram of parts of two logic modules 11 and 12 of FPGA 1. The output node 13 of the output device 14 of logic module 11 is coupled to input lead 15 of an input logic device 16 of logic module 12 via high voltage output protection transistors 17 and 18, horizontally extending signal conductor 19, programmed cross antifuse 20, vertically extending signal conductor 21, programmed cross antifuse 22, horizontally extending signal conductor 23, programmed cross antifuse 24, vertically extending signal conductor 25, programmed cross antifuse 26, and horizontally extending signal conductor 27. This particular path through the interconnect structure is chosen for explanatory purposes. Input logic device 16 drives a select input of a three multiplexer structure such as disclosed in FIG. 3E of U.S. Pat. No. 5,424,655 (the subject matter of which is incorporated herein by reference).
During antifuse programming, a programming voltage (for example, 10.5 volts) may be present on various of the signal conductors of the interconnect structure. For example, a 10.5 volt programming voltage may be placed on horizontal signal conductor 19 while vertical signal conductor 21 is grounded such that the 10.5 programming voltage appears across cross antifuse 20 such that antifuse 20 is programmed. Without high voltage output protection transistors 17 and 18 isolating the high programming voltage from the low voltage logic transistors 28 and 29 of the output device 14, the low voltage logic transistors 28 and 29 could be damaged.
FIG. 3 illustrates one way such damage could occur. To impose the 10.5 volt programming voltage across cross antifuse 20, a 10.5 volt programming voltage is placed on horizontal signal conductor 19. FIG. 4 is a cross-sectional diagram of the low voltage P-channel pull-up transistor 28 of the output device 14 of logic module 11. Because the low voltage logic transistors 28 and 29 of the output device of the logic module are powered by a lower supply voltage (in this case 3.3 volts) and the N well 29A (transistor body) of the P-channel pull-up transistor 28 is coupled via contact 30 to the source region 31, the N well 29A is coupled to 3.3 volts and the P+ drain region 32A to N well 29A boundary is forward biased. To avoid this potentially harmful situation as well as other problems, the high voltage output protection transistors 17 and 18 are provided. The high voltage output protection transistors 17 and 18 are nonconductive during antifuse programming, thereby protecting the low voltage logic transistors 28 and 29 from damage. During normal circuit operation of the FPGA, the high voltage output protection transistors 17 and 18 are made conductive, thereby connecting the output node 13 of the output device 14 to the horizontally extending signal conductor 19. If only high voltage output protection transistor 17 were provided, then a digital logic high signal passing from output node 13 to horizontal signal conductor 19 would suffer a threshold drop due to the fact that the gate of transistor 17 is biased at supply voltage VCC. Another high voltage output protection transistor 18 whose gate is driven with a voltage that is greater than VCC is therefore provided. This higher charge pump voltage (VCP) is needed during normal circuit operation and is provided by an on-chip charge pump (not shown). The charge pump consumes space on the integrated circuit and consumes approximately 500 microamperes maximum of standby current (over the 0-70 degrees Celsius range) even if the other digital logic of the FPGA is sitting idle and not switching. This standby current drain is highly undesirable for low power and battery applications.
If the low voltage logic transistors 28 and 29 did not need to be protected from the high voltage on the signal conductors during programming, then two high voltage output protection transistors could be omitted from each logic module output. This would make the logic module smaller. Moreover, the charge pump could be omitted. This reduces the standby current consumption of the FPGA.
During power up of the FPGA, the supply voltage VCC and the charge pump voltage VCP supplied to the high voltage output protection transistors 17 and 18 will be at intermediate voltages for some period of time. These protection transistors 17 and 18 will therefore not be fully conductive and the output devices of the logic modules will not be fully coupled to the signal conductors of the interconnect structure. As a result, intermediate voltages may be present on the signal conductors of the interconnect structure and on the input leads of the logic module input devices. These intermediate voltages may cause an undesirable power current spike during power up through logic module input devices.
FIG. 5 (Prior Art) is a transistor level diagram of the NAND gate logic module input device 16. Input device 16 has three non-inverting input leads 32-34 and four inverting input leads 35, 15, 36 and 37. Transistors 38-45 form a four input NOR gate and transistors 46-53 form a four input NAND gate. If all the input leads 35, 15, 36 and 37 were, for example, floating and at intermediate voltage levels, all of P-channel transistors 38-41 would be partially conductive and all of N-channel transistors 42-45 would be partially conductive. Accordingly, a current would flow from supply voltage VCC at the source of transistor 38 (for example, 3.3 volts) through transistors 38-45 to ground at the source of transistors 42-45.
To prevent this situation, one of the input leads 37 is coupled to a hard wired internal disable signal (INTDIS). This INTDIS signal is initially high (substantially equal to VCC as VCC rises) during the power up period when the intermediate voltages may be present on the input device 16 input leads. For additional information on internal disable circuitry, see U.S. patent application Ser. No. 08/775,984 entitled "Power-Up Circuit For Field Programmable Gate Array," filed Jan. 3, 1997 by James M. Apland et al., now U.S. Pat No. 5,828,538, issued Oct. 27, 1998 (the subject matter of which is incorporated herein by reference). Providing this extra INTDIS signal adds two additional transistors 41 and 42 to each such logic module input device as well as the associated interconnect to connect all the logic module input devices to an INTDIS signal conductor. If the INTDIS signal were not needed, then transistors 41 and 42 could be omitted resulting in considerable die area savings.
Although the internal circuitry of FPGA 1 operates with a power supply voltage VCC (for example, 3.3 volts), the FPGA may be placed on a printed circuit board with other logic that has a higher power supply voltage. This other logic may therefore drive a digital logic high signal of, for example, 5.0 volts onto terminals of the FPGA. It is desired that the FPGA be able to receive such high voltage logic signals without failing, being damaged, or sinking too much current.
FIG. 6 (Prior Art) is a simplified diagram illustrating the output driver 4 including a P-channel pull-up transistor 54 and an N-channel pull-down transistor 55 as well as output terminal 5. Consider the situation where logic external to the FPGA drives a digital logic high of 5.0 volts onto output terminal 5, the output driver is powered with a lower supply voltage (for example, 3.3 volts), and the semiconductor body into which the P-channel pull-up transistor 54 is formed is biased at 3.3 volts. FIG. 7 is a cross-sectional diagram illustrating P-channel pull-up transistor 54 in this situation. The P+ drain region 56 to N well 57 boundary will be forward biased giving rise to a possible large flow of current 58 into output driver 4. Such a forward bias situation could damage the FPGA and/or clamp the voltage to which the external logic can drive terminal 5 for a digital logic level high.
High voltage compatibility power input terminal (HVC) 8 is therefore provided. If external logic is to be able to drive terminal 5 to a 5.0 volt digital logic high level, for example, then HVC terminal 8 is coupled to a 5.0 volt supply and the HVC terminal is coupled to the semiconductor body (N well 57) of the P-channel pull-up transistor 54 of the output driver 4. With N well 57 biased to 5.0 volts, the P+ drain to N well boundary is not forward biased when the external logic attempts to drive terminal 5 to 5.0 volts.
FIGS. 1, 6 and 7 illustrate output driver 4 in simplified form to clarify the explanation. FIG. 8 (Prior Art) is a circuit diagram of an actual output driver circuit. The output driver circuit includes a non-inverting input lead 59, an enable input lead 60 and an output lead 61. The semiconductor body of P-channel pull-up transistor 54 is coupled to the high voltage compatible input power terminal HVC 8 whereas its source is coupled to supply voltage power input terminal VCC 6. The circuitry 62 in the dashed box is a level shifting circuit.